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1745D–ATARM–04-Nov-05
AT91M55800A
19.5 TC User Interface
TC Block 0 Base Address: 0xFFFD0000 (Code Label TCB0_BASE)
TC Block 1 Base Address: 0xFFFD4000 (Code Label TCB1_BASE)
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC Channels are controlled
by the registers listed in Table 19-3. The offset of each of the Channel registers in Table 19-3 is in relation to the offset of
the corresponding channel as mentioned in Table 19-2.
Note: 1. Read-only if WAVE = 0
Table 19-2. TC Global Memory Map
Offset Channel/Register Name Access Reset State
0x00 TC Channel 0 See Table 19-3
0x40 TC Channel 1 See Table 19-3
0x80 TC Channel 2 See Table 19-3
0xC0 TC Block Control Register TC_BCR Write-only –
0xC4 TC Block Mode Register TC_BMR Read/Write 0
Table 19-3. TC Channel Memory Map
Offset Register Name Access Reset State
0x00 Channel Control Register TC_CCR Write-only –
0x04 Channel Mode Register TC_CMR Read/Write 0
0x08 Reserved –
0x0C Reserved –
0x10 Counter Value TC_CV Read/Write 0
0x14 Register A TC_RA Read/Write
(1)
0
0x18 Register B TC_RB Read/Write
(1)
0
0x1C Register C TC_RC Read/Write 0
0x20 Status Register TC_SR Read-only –
0x24 Interrupt Enable Register TC_IER Write-only –
0x28 Interrupt Disable Register TC_IDR Write-only –
0x2C Interrupt Mask Register TC_IMR Read-only 0