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1745D–ATARM–04-Nov-05
AT91M55800A
12.9.3 APMC System Clock Status Register
Register Name: APMC_SCSR
Access Type: Read-only
Reset Value: 0x1
Offset: 0x08
• CPU: System Clock Status Bit
0 = System Clock is disabled.
1 = System Clock is enabled.
12.9.4 APMC Peripheral Clock Enable Register
Register Name: APMC_PCER
Access Type: Write-only
Offset: 0x10
• Peripheral Clock Enable (per peripheral)
0 = No effect.
1 = Enables the peripheral clock.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
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CPU
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
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DAC1 DAC0 ADC1
15 14 13 12 11 10 9 8
ADC0 PIOB PIOA
–
TC5 TC4 TC3 TC2
76543210
TC1 TC0 SPI US2 US1 US0
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