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1745D–ATARM–04-Nov-05
AT91M55800A
20.7.13 SPI Chip Select Register
Register Name: SP_CSR0.. SP_CSR3
Access Type: Read/Write
Reset State: 0
Offset: 0x30......0x3C
• CPOL: Clock Polarity (Code Label SP_CPOL)
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce a desired
clock/data relationship between master and slave devices.
• NCPHA: Clock Phase (Code Label SP_NCPHA)
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce a desired clock/data relationship between master and slave devices.
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS
– –
NCPHA CPOL
BITS[3:0] Bits Per Transfer Code Label: SP_BITS
0000 8 SP_BITS_8
0001 9 SP_BITS_9
0010 10 SP_BITS_10
0011 11 SP_BITS_11
0100 12 SP_BITS_12
0101 13 SP_BITS_13
0110 14 SP_BITS_14
0111 15 SP_BITS_15
1000 16 SP_BITS_16
1001 Reserved –
1010 Reserved –
1011 Reserved –
1100 Reserved –
1101 Reserved –
1110 Reserved –
1111 Reserved –