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1745D–ATARM–04-Nov-05
AT91M55800A
12.9.1 APMC System Clock Enable Register
Register Name: APMC_SCER
Access Type: Write-only
Offset: 0x00
• CPU: System Clock Enable Bit
0 = No effect.
1 = Enables the System Clock.
12.9.2 APMC System Clock Disable Register
Register Name: APMC_SCDR
Access Type: Write-only
Offset: 0x04
• CPU: System Clock Disable Bit
0 = No effect.
1 = Disables the System Clock.
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76543210
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CPU
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
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CPU