Filter
Top Products
195
1745D–ATARM–04-Nov-05
AT91M55800A
20.7.2 SPI Mode Register
Register Name: SP_MR
Access Type: Read/Write
Reset State: 0
Offset: 0x04
• MSTR: Master/Slave Mode (Code Label SP_MSTR)
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
MSTR configures the SPI Interface for either master or slave mode operation.
• PS: Peripheral Select
• PCSDEC: Chip Select Decode (Code Label SP_PCSDEC)
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder.
The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:
SP_CSR0defines peripheral chip select signals 0 to 3.
SP_CSR1defines peripheral chip select signals 4 to 7.
SP_CSR2defines peripheral chip select signals 8 to 11.
SP_CSR3defines peripheral chip select signals 12 to 15
(1)
.
Note: 1. The 16th state corresponds to a state in which all chip selects are inactive. This allows a dif-
ferent clock configuration to be defined by each chip select register.
• MCK32: Clock Selection (Code Label SP_DIV32)
0 = SPI Master Clock equals MCK.
1 = SPI Master Clock equals MCK/32.
• LLB: Local Loopback Enable (Code Label SP_LLB)
0 = Local loopback path disabled.
1 = Local loopback path enabled.
LLB controls the local loopback on the data serializer for testing in master mode only.
31 30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
– – – –
PCS
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
LLB
– – –
MCK32 PCSDEC PS MSTR
PS Selected PS Code Label: SP_PS
0 Fixed Peripheral Select SP_PS_FIXED
1 Variable Peripheral Select SP_PS_VARIABLE