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1745D–ATARM–04-Nov-05
AT91M55800A
22.2.2 DAC Mode Register
Register Name: DAC_MR
Access Type: Read/Write
Reset State: 0
Offset: 0x04
• TTRGEN: Timer Trigger Enable (Code Label DAC_TTRGEN_EN)
• TTRGSEL: Timer Trigger Selection
Only used if TTRGEN = 1
• RES: Resolution
31 30 29 28 27 26 25 24
– – – – – – – –
23 22 21 20 19 18 17 16
– – – – – – – –
15 14 13 12 11 10 9 8
– – – – – – – –
7 6 5 4 3 2 1 0
– –
–
RES TTRGSEL TTRGEN
TTRGEN Selected TTRGEN Code Label
0
The data written into the Data Holding Register (DAC_DHR) is transferred
one main clock cycle later to the data output register (DAC_DOR).
DAC_TTRGEN_DIS
1
The data transfer from the DAC_DHR to the DAC_DOR is synchronized
by the timer trigger.
DAC_TTRGEN_EN
TTRGSEL Selected Timer Trigger
Code Label
DAC_TTRGSEL
000 TIOA0 DAC_TRG_TIOA0
001 TIOA1 DAC_TRG_TIOA1
010 TIOA2 DAC_TRG_TIOA2
011 TIOA3 DAC_TRG_TIOA3
100 TIOA4 DAC_TRG_TIOA4
101 TIOA5 DAC_TRG_TIOA5
11X Reserved –
RES Selected RES Code Label
0 10-bit resolution DAC_10_BIT_RES
1 8-bit resolution DAC_8_BIT_RES