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1745D–ATARM–04-Nov-05
AT91M55800A
indicates the number of data float waits to be inserted and represents the time allowed for the
data output to go high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long t
DF
will not slow down the execution of a program from internal
memory.
The EBI keeps track of the programmed external data float time during internal accesses, to
ensure that the external memory system is not accessed while it is still busy.
Internal memory accesses and consecutive accesses to the same external memory do not
have added Data Float wait states.
Figure 11-12. Data Float Output Time
Notes: 1. Early Read Protocol
2. Standard Read Protocol
11.8.3 External Wait
The NWAIT input can be used to add wait states at any time. NWAIT is active low and is
detected on the rising edge of the clock.
If NWAIT is low at the rising edge of the clock, the EBI adds a wait state and changes neither
the output signals nor its internal counters and state. When NWAIT is de-asserted, the EBI fin-
ishes the access sequence.
The NWAIT signal must meet setup and hold requirements on the rising edge of the clock.
ADDR
NRD
D0-D15
MCK
t
DF
(1) (2)
NCS