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1745D–ATARM–04-Nov-05
AT91M55800A
5. Architectural Overview
The AT91M55800A microcontroller integrates an ARM7TDMI with its embedded ICE inter-
face, memories and peripherals. Its architecture consists of two main buses, the Advanced
System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum perfor-
mance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor
with the on-chip 32-bit memories, the External Bus Interface (EBI) and the AMBA
™
Bridge.
The AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and
optimized for low power consumption.
The AT91M55800A microcontroller implements the ICE port of the ARM7TDMI processor on
dedicated pins, offering a complete, low cost and easy-to-use debug solution for target
debugging.
5.1 Memory
The AT91M55800A microcontroller embeds 8K bytes of internal SRAM. The internal memory
is directly connected to the 32-bit data bus and is single-cycle accessible.
The AT91M55800A microcontroller features an External Bus Interface (EBI), which enables
connection of external memories and application-specific peripherals. The EBI supports 8- or
16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI imple-
ments the early read protocol, enabling faster memory accesses than standard memory
interfaces.
5.2 Peripherals
The AT91M55800A microcontroller integrates several peripherals, which are classified as sys-
tem or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and
can be programmed with a minimum number of instructions. The peripheral register set is
composed of control, mode, data, status and enable/disable/status registers.
An on-chip, 8-channel Peripheral Data Controller (PDC) transfers data between the on-chip
USARTs/SPI and the on and off-chip memories without processor intervention. One PDC
channel is connected to the receiving channel and one to the transmitting channel of each
USART and of the SPI.
Most importantly, the PDC removes the processor interrupt handling overhead and signifi-
cantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K
contiguous bytes. As a result, the performance of the microcontroller is increased and the
power consumption reduced.
5.2.1 System Peripherals
The External Bus Interface (EBI) controls the external memory and peripheral devices via an
8- or 16-bit data bus and is programmed through the APB. Each chip select line has its own
programming register.
The Advanced Power Management Controller (APMC) optimizes power consumption of the
product by controlling the clocking elements such as the oscillators and the PLL, system and
user peripheral clocks, and the power supplies.
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the inter-
nal peripherals and the eight external interrupt lines (including the FIQ), to provide an interrupt
and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and,
using the Auto-vectoring feature, reduces the interrupt latency time.