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ALIGNMENT AND TEST PROCEDURES
7-29
March 1999
Part No. 001-2009-600
Figure 7-29 MAIN PROCESSOR CARD ALIGNMENT POINTS
P1
1
33
64
32
1234
1234567
8
S2
1
2
3
4
5
6
110
5
6
J4
DS1
CR1
CR2
CR4
J1
1
7A
2
6
8B
S1
J2
1
23
1
2
14
13
J3
GRN
YEL
YEL
RED
RED
COMPUTER I/O
PROGRAMMING
CONNECTOR
RESET
ON
ON
S3
1
2
3
J5
1
2
3
J6
CR5
CR3
76800
38400
19200
9600
4800
2400
1200
11.059
12
HSDB
MULTI-NET
EPROM MEMORY
LOADING
WATCHDOG
BALANCED RX/TX
- MPC OPERATIONAL (BLINKING)
- ON = HIGH POWER, OFF = LOW POWER
- ON = LTR, OFF = MULTI-NET
USED WITH DS1 FOR ALARMS
USED WITH CR3/4 FOR ALARMS
+5V
+12V
MEMORY
SELECT