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14 www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller
UG129 (v1.1.2) June 24, 2008
Chapter 1: Introduction
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Program Counter (PC)
The Program Counter (PC) points to the next instruction to be executed. By default, the PC
automatically increments to the next instruction location when executing an instruction.
Only the JUMP, CALL, RETURN, and RETURNI instructions and the Interrupt and Reset
Events modify the default behavior. The PC cannot be directly modified by the application
code; computed jump instructions are not supported.
The 10-bit PC supports a maximum code space of 1,024 instructions (000 to 3FF hex). If the
PC reaches the top of the memory at 3FF hex, it rolls over to location 000.
Program Flow Control
The default execution sequence of the program can be modified using conditional and
non-conditional program flow control instructions.
The JUMP instructions specify an absolute address anywhere in the 1,024-instruction
program space.
CALL and RETURN instructions provide subroutine facilities for commonly used sections of
code. A CALL instruction specifies the absolute start address of a subroutine, while the
return address is automatically preserved on the CALL/RETURN stack.
If the interrupt input is enabled, an Interrupt Event also preserves the address of the
preempted instruction on the CALL/RETURN stack while the PC is loaded with the
interrupt vector, 3FF hex. Use the RETURNI instruction instead of the RETURN instruction
to return from the interrupt service routine (ISR).
CALL/RETURN Stack
The CALL/RETURN hardware stack stores up to 31 instruction addresses, enabling
nested CALL sequences up to 31 levels deep. Since the stack is also used during an
interrupt operation, at least one of these levels should be reserved when interrupts are
enabled.
The stack is implemented as a separate cyclic buffer. When the stack is full, it overwrites
the oldest value. Consequently, there are no instructions to control the stack or the stack
pointer. No program memory is required for the stack.
Interrupts
The PicoBlaze microcontroller has an optional INTERRUPT input, allowing the PicoBlaze
microcontroller to handle asynchronous external events. In this context, “asynchronous”
relates to interrupts occuring at any time during an instruction cycle. However,
recommended design practice is to synchronize all inputs to the PicoBlaze controller using
the clock input.
The PicoBlaze microcontroller responds to interrupts quickly in just five clock cycles.
See Chapter 4, “Interrupts,” for more information.
Reset
The PicoBlaze microcontroller is automatically reset immediately after the FPGA
configuration process completes. After configuration, the RESET input forces the processor
into the initial state. The PC is reset to address 0, the flags are cleared, interrupts are
disabled, and the CALL/RETURN stack is reset.