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112 www.xilinx.com PicoBlaze 8-bit Embedded Microcontroller
UG129 (v1.1.2) June 24, 2008
Appendix : PicoBlaze Instruction Set and Event Reference
R
Registers/Flags Altered
Registers: sX, PC
Flags: CARRY, ZERO
STORE sX, Operand — Write Register sX Value to Scratchpad RAM
Location
The STORE instruction writes register sX to the scratchpad RAM location specified by
Operand, as shown in Figure C-8. There are 64 scratchpad RAM locations. The two most-
significant bits of Operand, bits 7 and 6, are discarded and the RAM address is truncated to
the least-significant six bits of Operand, bits 5 to bit 0. Consequently, a STORE operation to
address FF is equivalent to a STORE operation to address 3F.
Examples
STORE sX, (sY) ; Write register sX to scratchpad RAM location
; specified by the contents of register sY
STORE sX, kk ; Write register sX to scratchpad RAM location
; specified by the immediate constant kk
Pseudocode
Scratchpad_RAM[Operand[5:0]] Å sX
PC Å PC + 1
Registers/Flags Altered
Registers: sX, PC
Flags: None
Notes
pBlazIDE Equivalent: The instruction mnemonic, STORE, is the same for both KCPSM3
and pBlazIDE. However, the instruction syntax for indirect addressing is slightly different.
The KCPSM3 syntax places parentheses around the indirect address while the pBlazIDE
syntax uses no parentheses.
Figure C-8: STORE Operation
Register sY or
Literal kk
Register sX
DATA_IN[7:0]
ADDRESS[5:0]
DATA_OUT[7:0]
64-Byte Scratchpad RAM
WRITE_ENABLETRUE
[5:0]
[7]
[6]
UG129_aC_10_051604