NEC ND-71762(E) Telephone User Manual


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ND-71762 (E) CHAPTER 4
Page 37
Issue 2
INSTALLATION PROCEDURE
Figure 4-6 PLO Pin Assignments for Receiving Clock (1-IMG System)
00 0102 03 04 050607 080910 11 12 13 1415 161718 1920 21 2223
Front View
PIM0
Universal Slots Universal Slots
PIN
No.
26
27
28
29
30
31
32
33
LEAD
NAME
DCSB0
DIU0B0
DIU1B0
DIU2B0
DIU3B0
SYN0B0
SYN1B0
LEAD
NAME
DCSA0
DIU0A0
DIU1A0
DIU2A0
DIU3A0
SYN0A0
SYN1A0
PIN
No.
1
2
3
4
5
6
7
8
PIN
No.
26
27
28
29
30
31
32
33
LEAD
NAME
DCSB0
DIU0B0
DIU1B0
DIU2B0
DIU3B0
SYN0B0
SYN1B0
LEAD
NAME
DCSA0
DIU0A0
DIU1A0
DIU2A0
DIU3A0
SYN0A0
SYN1A0
PIN
No.
1
2
3
4
5
6
7
8
40
41
42
43
44
45
46
47
48
49
50
15
16
17
18
19
20
21
22
23
24
25
DCSB1
DIU0B1
DIU1B1
DIU2B1
DIU3B1
SYN0B1
SYN1B1
DCSA1
DIU0A1
DIU1A1
DIU2A1
DIU3A1
SYN0A1
SYN1A1
40
41
42
43
44
45
46
47
48
49
50
15
16
17
18
19
20
21
22
23
24
25
DCSB1
DIU0B1
DIU1B1
DIU2B1
DIU3B1
SYN0B1
SYN1B1
DCSA1
DIU0A1
DIU1A1
DIU2A1
DIU3A1
SYN0A1
SYN1A1
PLO Connector PLO Connector
for PLO
equipped
with TSW #0
for PLO
equipped
with TSW #0
for PLO
equipped
with TSW #1
for PLO
equipped
with TSW #1
for receiveing clock from
a High-Stability Oscillator
for distributing clock from
a digital interface
Backplane
Since PLO circuit is equipped with TSW card, PLO input leads appear on the LT connector labeled PLO.
TSW mounting slots
TSW card is mounted in slots 13 and 14
of PIM0.
LT cable connector
Connect an LT cable to the connector labeled
PLO on PIM0 backplane.
PLO connector Pin Assignment
Pins are assigned as follows on PLO connector. When clock is distributed from a digital interface, use one pair
of DIUxxx leads among a maximum of 4 inputs. DIU leads have the following precedence: DIU0xx(High)
DIU3xx(Low). On the contrary, to receive clock from an external high-stability osillator, use DCSxx leads.
TSW
TSW
PIM0
PLO
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