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4–20
In the analog mode, (MODE bit set low), PAEN is high whenever TXEN is active and SYNOL is low. The
SYNOL input can be used as an indication to the TCM4300 that the external synthesizers are out of lock.
The PAEN signal is gated by SYNOL to prevent off-channel transmissions.
The TXEN, IQRXEN, FMVOX, and MODE signals are generated by sampling the corresponding bits of the
DStatCtrl register with the internal SINT. The effect of a write to the DStatCtrl register on these signals does
not appear until the next SINT after the write.
4.14 Microcontroller-DSP Communications
The microcontroller and the DSP communicate by means of two separate 32-byte first-in first-out (FIFO)
buffers. Figure 4–10 illustrates this scheme. The microcontroller writes to FIFO A, but data read from the
same address comes from FIFO B. On the DSP side, the situation is reversed.
Send CINT,
CINT Status,
Clear DINT
FIFO A
FIFO B
Send DINT,
DINT Status,
Clear CINT
DSP
µC
8
8
DINT
CINT
Figure 4–10. Microcontroller-DSP Data Buffers
To send data to the DSP, the microcontroller writes data to FIFO A. To indicate to the DSP that FIFO A is
ready to be read, the microcontroller writes a 1 to the Send-C bit of the microcontroller interrupt control
register MIntCtrl. When this happens, the DSP interrupt line CINT goes active, signaling to the DSP that data
is waiting. At the same time, the value that can be read from the Clear-C bit in the DIntCtrl register goes from
0 to 1, indicating that the interrupt is pending. When the DSP writes a 1 to the Clear-C bit, the CINT line
returns to the inactive state and the value that can be read from Clear-C is 0. The microcontroller cannot
deassert the CINT line.
The microcontroller-DSP communications interface is symmetric. Data sent from the DSP to the
microcontroller is handled as described above, with the roles of A and B FIFOs and C and D bits and
interrupts reversed. When the number of reads exceeds the number of writes from the other side, the values
read are undefined.