Filter
Top Products
3–4
3.4 TCM4300 to Microcontroller Interface Timing Requirements (Intel Read
Cycle) (see Figure 3–4 and Note 3)
PARAMETER
ALTERNATE
SYMBOL
MIN MAX
UNIT
t
su(RA)
Setup time, read address MCA stable before falling edge of
strobe MCDS
TRA
(SU)
0 ns
t
h(RA)
Hold time, read address MCA stable after rising edge of
strobe MCDS
TRA
(HO)
10 ns
t
en(RD)
Enable time, read data on falling edge of strobe MCDS to
TCM4300 driving data bus MCD
TRD
(EN)
10 ns
t
v(RD)
Valid time, read data on falling edge of strobe MCDS to
valid data MCD
TRD
(DV)
50 ns
t
inv
Data MCD invalid after rising edge of strobe MCDS TRD
(INV)
10 ns
t
dis(RD)
Disable time, read data. TCM4300 releases MCD data bus
after rising edge of strobe MCDS
TRD
(DIS)
28 ns
t
su(CS)
Setup time, chip select MCCSH and MCCSL stable before
falling edge of strobe MCDS
TCS
(SU)
0 ns
t
h(CS)
Hold time, chip select MCCSH and MCCSL stable before
rising edge of strobe MCDS
TCS
(HO)
0 ns
NOTE 3: Timings are based upon Intel 80C186 (16 MHz).
MCA4–MCA0
MCD7–MCD0
MCDS
(see Note A)
MCRW
t
su(RA)
10%
90%
90%
10%
t
h(RA)
t
v(RD)
t
en(RD)
t
dis(RD)
t
inv
t
su(CS)
t
h(CS)
MCCSH
MCCSL
90% 90%
10% 10%
NOTE A: Chip selection is defined as both MCCS and MCDS active.
Figure 3–4. Microcontroller Interface Timing Requirements
(Intel Configuration Read Cycle, MTS [1:0] = 00)