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40 Avaya Application Solutions IP Telephony Deployment Guide
The G700 motherboard hardware design involves three major blocks:
● A DSP engine and associated packet processor complex. This complex performs IP/UDP/
RTP processing, echo cancellation, G.711 A/µ, G.729 (with or without silence
suppression), fax relay, silence suppression, jitter buffer management, packet loss
concealment, and so on.
● A Gateway Processor complex. This complex is the master controller of the Gateway, and
controls all resources inside the Gateway under the direction of the Gateway Controller.
Examples of the functions implemented here include the Media Module Manager, Tone/
Clock, PKTINT, Announcements (record/playback), and H.248 signaling to the Gateway
Controller.
● An Intel 960 processor complex. This complex is based on the architecture of the P330
data switch. This complex provides an eight-port Layer 2 switch function, and the i960
manages the Expansion and Cascade modules.
These major blocks are interconnected through two major communication paths: an Ethernet
link and the Time Division Multiplexed (TDM) bus similar to that in a port network. In addition,
the motherboard provides electrical and physical connectivity for four media modules.
VoIP Engine complex
The internal VoIP Engine block is where PCM voice samples are encoded and put into IP
packets, and vice-versa. This block implements all the functions that are normally associated
with a Gateway. Such functions include packet loss concealment, jitter buffer management,
transcoding, and so on.
The VoIP Engine of the G700 motherboard has three major components: two Digital Signal
Processors (DSPs), and a Motorola MPC8260 processor. The DSPs together provide the same
VoIP channel capacities as the TN2302AP IP Media Processor circuit pack: 64 G.711 channels
or 32 G.729 channels.
Each additional VoIP Media Module (MM760) increases the VoIP channel capacity of a G700
media gateway by the equivalent of a TN2302AP circuit pack.
The G700 Media Gateway Processor
The G700 Media Gateway Processor (MGP) is the master controller of the Media Gateway. The
Motorola 860T processor in this complex implements the H.248 protocol to communicate with
the Gateway Controller. Under the direction of the Gateway Controller, the 860T Gateway
Processor controls the flow of data through the Gateway. The 860T processor communicates
with other processors in the system – the VoIP Engine processor, the i960 processor, and any
processors on media modules – through either the control channel of the TDM bus, or an
Ethernet link (the i960 processor connects only through Ethernet).
Functions implemented within the MGP complex include:
● Management of the media modules (reset control, board and interface insertion, and so on)
● Termination of the LAPD protocol running on the D-channel of E1/T1 trunks and BRI lines
and trunks (32 channels capacity).