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low-pass filter and UHF signal are high-pass filter, and then
applied to the VHF and UHF power amplifier circuit sepa-
rately.
4-2-7 POWER AMPLIFIER CIRCUIT (PA UNIT)
The power amplifier circuit amplifies the RF signals to the
specified output power.
(1) VHF power amplifier circuit
The RF signal from the low-pass filter circuit is applied to the
VHF power amplifier circuit (Q651, Q652) to obtain a stable
100 W of RF output power. The amplified RF signal is
applied to the antenna connector (CHASSIS; J1) via the
power detector (D720, D721), transmit/receive switching
relay (RL700) and low-pass filter (L723–L721, C728–C726,
C728) circuits.
(2) UHF power amplifier circuit
The RF signal from the high-pass filter is applied to the
UHF power amplifier circuit (Q151, Q152) to obtain a sta-
ble 75 W of RF output power. The amplified RF signal is
applied to the antenna connector (CHASSIS; J2) via the
transmit/receive switching circuit (D182–D185), low-pass
filter (L181, L180, C188–C184) and power detector (D180,
D181) circuits.
4-2-8 ALC CIRCUIT (PA AND MAIN UNITS)
The ALC (Automatic Level Control) circuit protects the
power amplifiers (PA unit; Q651, Q652 for VHF and Q151,
Q152 for UHF) from a mismatched output load. Also, the
ALC circuit controls the gain of the transmit IF amplifier in
order for the transceiver to output even when the supplied
voltage shifts, etc.
The RF power level is detected at the power detector circuit
(PA unit; D720–D721 for VHF, D180, D181 for UHF) to be
converted into DC voltages. The detected voltage (VFOR for
VHF or UFOR for UHF) is passed through the switching
diode, and are then applied to the differential amplifier
(MAIN unit; IC1601b) via the FOR line. A reference voltage
(POCV) for IC1601b is controlled by the [RF PWR] control
to output reference voltages. The output voltage is applied
to the transmit IF amplifier circuit (MAIN unit; Q1) as an ALC
signal to control the amplifier gain.
When the VFOR/UFOR voltage increased, the output from
the differential amplifier will be decrease to reduce the IF
amplifier gain. This adjusts the RF output power until the
VFOR/UFOR and POCV voltage are well balanced.
4-2-9 APC CIRCUIT (MAIN UNIT)
The APC (Automatic Power Control) circuit protects the
power amplifiers on the PA unit from excessive current.
Current drain of power amplifiers is detected by voltage
drops at a resistor (PA unit; R305) between VCC and PAHV
lines. The original voltage (ICH) and dropped voltage (ICL)
are applied to the APC differential amplifier (MAIN unit;
IC1601d).
The signal output from the differential amplifier reduces IF
amplifier gain until these voltages are well-balanced.
4-3 PLL CIRCUITS
IC-910H contains 2 PLL circuits and 1 local oscillator. The
VHF and UHF PLL circuits adopt “Icom’s original I-loop PLL”
to obtain very fast lock up times.
4-3-1 VHF PLL CIRCUIT (PLL UNIT)
The VHF PLL circuit generates the 1st LO frequency, and
the signal is applied to the VHF 1st mixer circuit in the PA
unit as the “A1LO” signal. The PLL circuit consists of a VCO,
prescaler and DDS circuits.
The signal generated at the VHF VCO circuit (Q191,
D191–D194) is amplified at the buffer amplifiers (Q192,
Q272), then applied to the prescaler circuit (IC271). The
prescaler circuit divides the applied signal, and outputs it to
the VHF DDS circuit (IC131) via the buffer amplifier (Q271).
The VHF DDS circuit generates digital signals using the
applied signals as a clock frequency. The phase detector
section in IC131 compares its phase with the reference fre-
quency that is generated at the reference oscillator (X512).
IC131 outputs off-phase components as pulse signals via
pins 51, 52.
The output pulses are converted into DC voltage at the loop
filter circuit (IC161a) and then applied to the VHF VCO cir-
cuit.
The D/A converter (R101–R124), low-pass filter
(L101–L103, C103–C110) and buffer amplifier (IC101) cir-
cuits are connected to the DDS output to convert the digital
oscillated signals into smooth analog signals.
4-3-2 UHF PLL CIRCUIT (PLL UNIT)
The UHF PLL circuit generates the 1st LO frequency, and
the signal is applied to the UHF 1st mixer circuit in the PA
unit as the “B1LO” signal. The PLL circuit consists of a VCO,
prescaler and DDS circuits.
The signal generated at the UHF VCO circuit (Q391,
D391–D394) is amplified at the buffer amplifiers (Q392,
Q472), then applied to the prescaler circuit (IC471). The
prescaler circuit divides the applied signal, and outputs it to
the UHF DDS circuit (IC331) via the buffer amplifier (Q471).
The D/A converter (R301–R324), low-pass filter
(L301–L303, C103–C311) and buffer amplifier (IC301) cir-
cuits are connected to the DDS output to convert the digital
oscillated signals into smooth analog signals.
4-4 UX-910 (1200 MHz BAND UNIT)
UX-910 is an optional 1200 MHz band unit for IC-910H. This
unit covers 1240–1300 MHz frequency range.
4-4-1 ANTENNA SWITCHING CIRCUIT (for RX)
Received signals from the antenna connector (CHASSIS;
J501) are applied to the transmit/receive switching circuit
(RL51).
The transmit/receive switching circuit leads receive signal to
the RF circuit while receiving. However, the circuit leads the
transmit signal from the RF power amplifier to the antenna
connector while transmitting.