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CIRCUIT DESCRIPTION
3-26
February 2001
Part No. 001-9800-001
This effectively AC grounds the receiver end of
the quarter-wave line through CR802 and C847. When
one end of a quarter-wave line is grounded, the other
end presents a high impedance to the quarter-wave
frequency. Therefore, the VCO signal is blocked from
the receiver by the quarter-wave line and has a low
impedance path through CR801 to the transmitter.
In the receive mode, both diodes are reverse
biased. The quarter-wave line is then no longer
grounded and provides a low impedance path to the
receiver while CR802 provides a high impedance into
the transmitter. L801/C846 and L800/C845 improve
isolation by neutralizing the slight capacitance of
CR801 and CR802 when they are reverse biased.
3.10.6 SYNTHESIZER INTEGRATED CIRCUIT
(U804)
Introduction
A block diagram of synthesizer IC U804 is shown
in Figure 3-5 on page 5-16. This integrated circuit
contains the following stages. The basic operation of
U804 was described in Section 3.10.1.
• Reference (R) divider
• Main divider
• Prescaler (÷64/65)
• Phase and lock detectors
• Charge pump and divider programming circuitry
Channel Programming
Channels are selected by programming the main
divider in U804 to divide by a certain number. This
programming is performed by the microcontroller over
the SPI serial data bus which consists of CLOCK,
DATA, and STROBE lines (see Section 3.3.1). As
previously described, this divider is programmed so
that when the VCO is oscillating on the correct
frequency, the fR and fV inputs to the phase detector
are the same frequency.
Operation
As stated in Section 3.10.1, the fR input to the
main phase detector is 50 kHz for all channels. The
reference oscillator frequency is divided by 350 (800
MHz) or 297 (900 MHz) to produce this signal. Frac-
tional-N division with modulo 5 or 8 selection allows
the loop frequency to be 5 or 8 times the channel
spacing. With 800 and 900 MHz channels, modulo 8 is
used to allow 6.25 kHz (12.5 kHz) channel spacing.
The fV input is produced by dividing down the
VCO frequency applied to the RF IN input. The first
divider which divides this signal is a prescaler which
is a special counter capable of operating at relatively
high frequencies. The prescaler divides by 64 and 65
which reduces a signal in the 800 MHz range down to
approximately 12 MHz. For each main divider output
pulse (fV), the prescaler divides by 65 for a certain
number of pulses and then 64 for an additional number
of pulses. The number counted in each mode is deter-
mined by the programming of the “N” and “A”
numbers. The basic operation is as follows:
The main divider begins counting down from the
“A” number. Then when zero is reached, it begins
counting down from the “N” number until zero is
reached. The cycle then repeats. While it is counting
down the “A” number, the prescaler divides by 65, and
while it is counting down the “N” number, it divides
by 64.
To illustrate the operation of these dividers, an
example will be used. Assume a transmit frequency of
813.4875 MHz is selected (800 MHz FCC channel
300). Since the VCO oscillates on the transmit
frequency in the transmit mode, this is the frequency
that must be produced by the VCO. To produce this
frequency, the “N” and “A” divide numbers are
programmed as follows:
N = 239 A = 13
To determine the overall divide number of the
prescaler and main divider, the number of prescaler
input pulses required to produce one main divider
output pulse can be determined. Although the “N”
number is 239 in this example, the actual divide
number is always two higher (241) because of reset
cycles and other effects. Therefore, the prescaler
divides by 65 for 13 x 65 or 845 input pulses. It then
divides by 64 for 241 x 64 or 15,424 input pulses.
Since the VCO frequency is not evenly divisible
by 50 kHz, there is also a fractional-N number
programmed that provides the required fractional
800/900 MHz SYNTHESIZER DESCRIPTION