Silicon Laboratories C8051F346 Two-Way Radio User Manual


 
Rev. 0.5 241
C8051F340/1/2/3/4/5/6/7
Table 20.1. SPI Slave Timing Parameters
Parameter Description Min Max Units
Master Mode Timing* (See Figure 20.8 and Figure 20.9)
T
MCKH
SCK High Time
1 x T
SYSCLK
ns
T
MCKL
SCK Low Time
1 x T
SYSCLK
ns
T
MIS
MISO Valid to SCK Shift Edge
1 x T
SYSCLK
+ 20
ns
T
MIH
SCK Shift Edge to MISO Change 0 ns
Slave Mode Timing* (See Figure 20.10 and Figure 20.11)
T
SE
NSS Falling to First SCK Edge
2 x T
SYSCLK
ns
T
SD
Last SCK Edge to NSS Rising
2 x T
SYSCLK
ns
T
SEZ
NSS Falling to MISO Valid
4 x T
SYSCLK
ns
T
SDZ
NSS Rising to MISO High-Z
4 x T
SYSCLK
ns
T
CKH
SCK High Time
5 x T
SYSCLK
ns
T
CKL
SCK Low Time
5 x T
SYSCLK
ns
T
SIS
MOSI Valid to SCK Sample Edge
2 x T
SYSCLK
ns
T
SIH
SCK Sample Edge to MOSI Change
2 x T
SYSCLK
ns
T
SOH
SCK Shift Edge to MISO Change
4 x T
SYSCLK
ns
T
SLH
Last SCK Edge to MISO Change (CKPHA = 1
ONLY)
6 x T
SYSCLK
8 x T
SYSCLK
ns
*Note: T
SYSCLK
is equal to one period of the device system clock (SYSCLK).