Silicon Laboratories C8051F345 Two-Way Radio User Manual


 
Rev. 0.5 251
C8051F340/1/2/3/4/5/6/7
21.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, USB Start-of-Frame (SOF) capture
mode, or Low-Frequency Oscillator (LFO) Falling Edge capture mode. The Timer 2 operation mode is
defined by the T2SPLIT (TMR2CN.3), T2CE (TMR2CN.4) bits, and T2CSS (TMR2CN.1) bits.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external preci
-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
21.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT = ‘0’ and T2CE = ‘0’, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in
Figure 21.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled, an interrupt
will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled and the TF2LEN
bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L) overflow from
0xFF to 0x00.
Figure 21.4. Timer 2 16-Bit Mode Block Diagram
External Clock / 8
SYSCLK / 12
SYSCLK
TMR2L TMR2H
TMR2RLL TMR2RLH
Reload
TCLK
0
1
TR2
TMR2CN
T2SPLIT
T2CSS
T2CE
TF2L
TF2H
T2XCLK
TR2
0
1
T2XCLK
Interrupt
TF2LEN
To ADC,
SMBus
To SMBus
TL2
Overflow
CKCON
T
3
M
H
T
3
M
L
S
C
A
0
S
C
A
1
T
0
M
T
2
M
H
T
2
M
L
T
1
M