Silicon Laboratories C8051F344 Two-Way Radio User Manual


 
Rev. 0.5 27
C8051F340/1/2/3/4/5/6/7
1.7. Serial Ports
The C8051F340/1/2/3/4/5/6/7 Family includes an SMBus/I2C interface, full-duplex UARTs, and an
Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.8. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur-
pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programma-
ble capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, a dedicated External Clock Input (ECI), the sys
-
tem clock, or the external oscillator clock source divided by 8. The external clock source selection is useful
for real-time clock functionality, where the PCA may be clocked by an external source while the internal
oscillator drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
Figure 1.8. PCA Block Diagram
Capture/Compare
Module 1
Capture/Compare
Module 0
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4 / WDT
CEX1
ECI
Crossbar
CEX2
CEX3
CEX4
CEX0
Port I/O
16-Bit Counter/Timer
PCA
CLOCK
MUX
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8