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C8051F340/1/2/3/4/5/6/7
6 Rev. 0.5
17.3.SMBus Operation ........................................................................................... 194
17.3.1.Arbitration............................................................................................... 195
17.3.2.Clock Low Extension.............................................................................. 196
17.3.3.SCL Low Timeout................................................................................... 196
17.3.4.SCL High (SMBus Free) Timeout .......................................................... 196
17.4.Using the SMBus............................................................................................ 196
17.4.1.SMBus Configuration Register............................................................... 198
17.4.2.SMB0CN Control Register ..................................................................... 201
17.4.3.Data Register ......................................................................................... 204
17.5.SMBus Transfer Modes.................................................................................. 204
17.5.1.Master Transmitter Mode....................................................................... 204
17.5.2.Master Receiver Mode........................................................................... 206
17.5.3.Slave Receiver Mode............................................................................. 207
17.5.4.Slave Transmitter Mode......................................................................... 208
17.6.SMBus Status Decoding................................................................................. 208
18.UART0.................................................................................................................... 211
18.1.Enhanced Baud Rate Generation................................................................... 212
18.2.Operational Modes ......................................................................................... 212
18.2.1.8-Bit UART............................................................................................. 213
18.2.2.9-Bit UART............................................................................................. 214
18.3.Multiprocessor Communications .................................................................... 214
19.UART1 (C8051F340/1/4/5 Only) ........................................................................... 219
19.1.Baud Rate Generator ..................................................................................... 220
19.2.Data Format.................................................................................................... 221
19.3.Configuration and Operation .......................................................................... 222
19.3.1.Data Transmission ................................................................................. 222
19.3.2.Data Reception ...................................................................................... 222
19.3.3.Multiprocessor Communications............................................................ 223
20.Enhanced Serial Peripheral Interface (SPI0)...................................................... 229
20.1.Signal Descriptions......................................................................................... 230
20.1.1.Master Out, Slave In (MOSI).................................................................. 230
20.1.2.Master In, Slave Out (MISO).................................................................. 230
20.1.3.Serial Clock (SCK) ................................................................................. 230
20.1.4.Slave Select (NSS) ................................................................................ 230
20.2.SPI0 Master Mode Operation......................................................................... 231
20.3.SPI0 Slave Mode Operation........................................................................... 233
20.4.SPI0 Interrupt Sources ................................................................................... 233
20.5.Serial Clock Timing......................................................................................... 234
20.6.SPI Special Function Registers...................................................................... 236
21.Timers.................................................................................................................... 243
21.1.Timer 0 and Timer 1 ....................................................................................... 243
21.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 243
21.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 244
21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 245
21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 246